module simple;
reg clock, reset, enable;
wire [3:0] counter_out;
wire test_clk;

initial begin: stop_at
#1000; $stop;
end

// Clock generator
always begin
#5 clock = ~clock; // Toggle clock every 5 ticks
end
   
initial begin: Init
$display ("time\t clk reset enable counter");	
$monitor ("%g\t %b   %b     %b      %b", $time, clock, reset, enable, counter_out);	
clock = 1;       // initial value of clock
reset = 0;       // initial value of reset
enable = 0;      // initial value of enable
#5 reset = 1;    // Assert the reset
#10 reset = 0;   // De-assert the reset
#10 enable = 1;  // Assert enable
#10000 enable = 0; // De-assert enable
#10000 $finish;      // Terminate simulation
end

first_counter U_counter (
clock,
reset,
enable,
counter_out
);

endmodule

module first_counter (
clock , // Clock input of the design
reset , // active high, synchronous Reset input
enable , // Active high enable signal for counter
counter_out // 4 bit vector output of the counter
); // End of port list
//-------------Input Ports-----------------------------
input clock ;
input reset ;
input enable ;
//-------------Output Ports----------------------------
output [3:0] counter_out ;
//-------------Input ports Data Type-------------------
// By rule all the input ports should be wires   
wire clock ;
wire reset ;
wire enable ;
//-------------Output Ports Data Type------------------
// Output port can be a storage element (reg) or a wire
reg [3:0] counter_out ;

always @ (posedge clock)
begin : COUNTER // Block Name

if (reset == 1'b1) begin
counter_out <= #1 4'b0000;
end

else if (enable == 1'b1) begin
counter_out <= #1 counter_out + 1;
end
end

endmodule // End of Module counter
